1. Field
This invention relates in general to electrostatic discharge (ESD) and more specifically to ESD circuitry arrangement in an integrated circuit.
2. Description of the Related Art
An integrated circuit may be subjected to a damaging Electrostatic Discharge (ESD) event in the manufacturing process, during assembly and testing, or in the ultimate system application. In conventional integrated circuit (IC) ESD protection schemes, special clamp circuits are often used to shunt ESD current between the power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) clamp circuit, typically comprises two parts: a trigger circuit and a large MOSFET clamp transistor. The conduction of the clamp transistor is controlled by the trigger circuit. Active MOSFET clamp circuits may be employed in networks distributed along the power buses to provide robust and consistent ESD protection for all the Input/Output (I/O) pads in the IC.
ESD circuitry can be implemented in many ways, but previous implementations require quite some added complexity in the supporting I/O library of standard cells (e.g. number of supported I/O cells increases significantly) and more complex I/O ring ESD integration rules. The placement of I/O cells to ensure compliance with design rules has largely been done manually.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.